1. Field of the Invention
The present invention relates to a BIST circuit for conducting a test on memory using a comparator-type signature analyzer.
2. Description of the Related Art
As one of test facilitating design techniques for large-scale integrated circuits (LSIs), there is a built-in self-test (BIST). This is for performing self diagnosis by providing a test circuit in the LSI and comparing a responded output of a circuit to be tested with respect to a test pattern generated by the test circuit, with an expected value.
FIG. 1 shows a block diagram of the configuration of a conventional random access memory built-in self-test (RAMBIST) circuit. As shown in FIG. 1, in a signature analyzer 1 of the conventional RAMBIST circuit, a 1-bit comparator 11 is provided for each of data output bits A[0] to A[n−1] in a RAM macro 2. In this configuration, the data output from each of the data output bits A[0] to A[n−1] in the RAM macro 2 is compared with expected value data generated by a data generator 3, for each corresponding bit by the 1-bit comparator 11. A controller 4 controls respective operations of the signature analyzer 1 and the data generator 3.
FIG. 2 shows a block diagram of another configuration of the conventional RAMBIST circuit. In the RAMBIST circuit shown in FIG. 2, a signature analyzer 1 is provided for each read port with respect to a multi-port type RAM macro 5 having a plurality of read ports (in the example shown in the figure, A and B ports). In this configuration, the data output from each read port of the RAM macro 5 is compared with the expected value data generated by a data generator 3, for each corresponding read port, by the respective signature analyzer 1. The controller 4 controls respective operations of the signature analyzers 1 and the data generator 3.
However, with a rapid progress of technology, the number of the RAM macros mounted on one chip is recently increasing. Accompanying this, the number of read ports and the number of data output bits increase considerably, causing a problem in that the chip area increases due to an increase in number of the signature analyzers.